A Scalable I/O Architecture for Wide I/O DRAM
Document Type
Conference Proceeding
Publication Date
8-7-2011
DOI
http://dx.doi.org/10.1109/MWSCAS.2011.6026682
Abstract
A 4 Gb DRAM architecture utilizing a scalable number of data pins is proposed. The architecture does not impact chip size and does not require additional metal layers. The 4 Gb DRAM measure 68.88 mm2 and achieves an array efficiency of 59.9%. This was accomplished by using a split bank, edge I/O interface, central row, and central column structures. The architecture coincides with the chip size and array efficiency measurements predicted by the ITRS for a 40 nm 2012 production DRAM architecture.
Publication Information
Harvard, Qawi and Baker, R. Jacob. (2011). "A Scalable I/O Architecture for Wide I/O DRAM". 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 1-4.
