Computer Science Faculty Publications and Presentations Copyright (c) 2013 Boise State University All rights reserved. http://scholarworks.boisestate.edu/cs_facpubs Recent documents in Computer Science Faculty Publications and Presentations en-us Sun, 27 Jan 2013 15:14:44 PST 3600 Visualizing Disease Incidence in the Context of Socioeconomic Factors http://scholarworks.boisestate.edu/cs_facpubs/23 http://scholarworks.boisestate.edu/cs_facpubs/23 Tue, 15 Jan 2013 11:43:38 PST Certain biological factors such as genetics, physical fitness, and lifestyle have been shown to influence an individual's risk of acquiring disease. But are there are other socioeconomic factors that influence disease incidence as well? In this paper, we introduce a visualization tool called Disease Trends that explores the associations and possible correlations between specific economic (personal income per capita), educational (percentage of adult population with a four year college degree), and environmental (air pollution level) factors with diabetes prevalence and cancer incidence rates across counties throughout the United States. It is structured as an interactive geographical visualization that displays disease incidence data as an interactive choropleth map and connects it with coordinated views of the socioeconomic variables for each county as the user scrolls over it. Additionally, the ability to compare and contrast counties as well as to interactively specify a region for comparison allows further examination of the data. This results in an informative overview of disease incidence trends that allows users to spot areas of interest and potentially pursue these areas further with more scientific research.

]]> Jared Shenson et al. Auto(mobile): Mobile Visual Interfaces for the Road http://scholarworks.boisestate.edu/cs_facpubs/22 http://scholarworks.boisestate.edu/cs_facpubs/22 Tue, 25 Sep 2012 10:43:33 PDT The increased prevalence of mobile touch screen interfaces in cars provides for new challenges in terms of optimizing safety, usability and affective response. While touch screens have certain usability benefits, the interfaces present significant visual attention demands from the driver. Suppose that you are traveling to an unfamiliar destination in your city to visit a friend. You know that she lives close to a popular landmark (mall, tourist attraction) and have visited that landmark several times. If you get directions from your GPS to visit your friend, it will most likely provide a shortest or fastest route, none of which will take into account the fact that you have visited the popular landmark several times. Additionally, the amount of navigational details that you would need to get to the popular landmark would be far fewer than the assistance you would need when you are driving in an unfamiliar region. By using context from the phone and car, more informed visual navigation applications can be created for a better user experience.

]]> Frederik Wiehr et al. RSVP: Remote Sensing Visualization Platform for Data Fusion http://scholarworks.boisestate.edu/cs_facpubs/21 http://scholarworks.boisestate.edu/cs_facpubs/21 Wed, 04 Apr 2012 12:34:55 PDT Remote sensing involves the acquisition of data in terms of images, point clouds and so on. One of the major challenges with remote sensing datasets is managing and understanding the massive amounts of data that is collected. In many instances, scientists acquire data for the same region using varied sensing devices. Scientists would like to fuse and examine this data acquired from different sensing devices to further explore the region under investigation. Immersive visualization has emerged as an ideal solution for three-dimensional exploration of multimodal remote sensing data. The ability to manipulate data interactively in true 3D (using stereo) with interfaces designed specifically for the immersive environment can significantly speed up the exploration process. We have developed a visualization platform that facilitates the fusion of multiple modalities of remote sensing data and allows a scientist to learn more about the data obtained from different sensing devices. It is currently being used in research labs at Idaho State University and at the Idaho National Labs.

]]> Vanessa Gertman et al. Reliable Sensor-to-Sink Data Transfer with Duty Cycles for Wireless Sensor Networks http://scholarworks.boisestate.edu/cs_facpubs/20 http://scholarworks.boisestate.edu/cs_facpubs/20 Tue, 21 Feb 2012 14:15:36 PST Wireless Sensor Networks (WSNs) are generally energy and resource constrained. However, packet level reliability is an important quality-of-service metric for any networking application. Existing sensor networking protocols that provide reliable data transfer for sensor-to-sink traffic either provide reliability at the event level or are not energy-efficient. Employing duty cycles improves energy-efficiency but significantly degrades the network performance, particularly packet delivery ratio for higher network traffic. We propose a cross layered approach that utilizes inactive nodes as monitors to assist in quick packet-loss detection and recovery while employing duty cycles for energy-efficiency. To improve packet level reliability, monitors passively overhear the communication of active nodes for detecting packet losses and also act as alternate forwarders to overcome congested spots. We implemented the proposed approach in ns-2 simulator and conducted extensive experimentation: results show that monitors provide a significant improvement in packet delivery ratio while providing energy savings.

]]> Sirisha Medidi et al. Extending Page Segmentation Algorithms for Mixed-Layout Document Processing http://scholarworks.boisestate.edu/cs_facpubs/19 http://scholarworks.boisestate.edu/cs_facpubs/19 Mon, 13 Feb 2012 11:46:33 PST The goal of this work is to add the capability to segment documents containing text, graphics, and pictures in the open source OCR engine OCRopus. To achieve this goal, OCRopus' RAST algorithm was improved to recognize non-text regions so that mixed content documents could be analyzed in addition to text-only documents. Also, a method for classifying text and non-text regions was developed and implemented for the Voronoi algorithm enabling users to perform OCR on documents processed by this method. Finally, both algorithms were modified to perform at a range of resolutions. Our testing showed an improvement of 15-40% for the RAST algorithm, giving it an average segmentation accuracy of about 80%. The Voronoi algorithm averaged around 70% accuracy on our test data. Depending on the particular layout and idiosyncracies of the documents to be digitized, however, either algorithm could be sufficiently accurate to be utilized.

]]> Amy Winder et al. An Overview of Static Pipelining http://scholarworks.boisestate.edu/cs_facpubs/18 http://scholarworks.boisestate.edu/cs_facpubs/18 Tue, 06 Dec 2011 12:47:10 PST A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. In this paper, we propose to respond to these conflicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefits of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can significantly reduce power consumption without adversely affecting performance.

]]> Ian Finlayson et al. Branch Elimination via Multi-Variable Condition Merging http://scholarworks.boisestate.edu/cs_facpubs/17 http://scholarworks.boisestate.edu/cs_facpubs/17 Wed, 28 Sep 2011 11:55:03 PDT Conditional branches are expensive. Branches require a significant percentage of execution cycles since they occur frequently and cause pipeline flushes when mispredicted. In addition, branches result in forks in the control flow, which can prevent other code-improving transformations from being applied. In this paper we describe profile-based techniques for replacing the execution of a set of two or more branches with a single branch on a conventional scalar processor. First, we gather profile information to detect the frequently executed paths in a program. Second, we detect sets of conditions in frequently executed paths that can be merged into a single condition. Third, we estimate the benefit of merging each set of conditions. Finally, we restructure the control flow to merge the sets that are deemed beneficial. The results show that eliminating branches by merging conditions can significantly reduce the number of conditional branches performed in non-numerical applications.

]]> William Kreahling et al. Tuning the WCET of Embedded Applications http://scholarworks.boisestate.edu/cs_facpubs/16 http://scholarworks.boisestate.edu/cs_facpubs/16 Wed, 28 Sep 2011 11:43:41 PDT It is advantageous to not only calculate the WCET of an application, but to also perform transformations to reduce the WCET since an application with a lower WCET will be less likely to violate its timing constraints. In this paper we describe an environment consisting of an interactive compilation system and a timing analyzer, where a user can interactively tune the WCET of an application. After each optimization phase is applied, the timing analyzer is automatically invoked to calculate the WCET of the function being tuned. Thus, a user can easily gauge the progress of reducing the WCET. In addition, the user can apply a genetic algorithm to search for an effective optimization sequence that best reduces the WCET. Using the genetic algorithm, we show that the WCET for a number of applications can be reduced by 7% on average as compared to the default batch optimization sequence.

]]> Wankang Zhao et al. An Interactive Simulation Tool for Complex Multilayer Dielectric Devices http://scholarworks.boisestate.edu/cs_facpubs/15 http://scholarworks.boisestate.edu/cs_facpubs/15 Fri, 02 Sep 2011 14:50:36 PDT Novel devices incorporating multiple layers of new materials increase the complexity of device structures, particularly in field-effect transistors, capacitors, and nonvolatile memory (NVM). The mounting complexity of these devices increases the difficulty of generating energy band diagrams and performing device parameter calculations whether these calculations are done by hand, using spreadsheets, or via mathematical programs. Although finite-element Poisson-Schrodinger equation solvers are available to perform the calculations, the cost and time spent learning them can be a hindrance. A straightforward GUI interactive simulation tool is presented that quickly calculates and displays energy bands, electric fields, potentials, and charge distributions for 1-D metal-multilayered-dielectrics-semiconductor stacks. Fixed charge can be inserted into dielectric layers. The freeware program calculates device parameters, (e.g., effective oxide thickness, flat-band voltage (VFB), threshold voltage (Vt), stack capacitance) and layer parameters (e.g., capacitance, potential, electric field, tunneling distance). Calculated data can be exported. Using the simulation tool, trap-based flash NVM is examined. Device performance characteristics such as the Vt and VFB shifts of three different stacks are examined. Comparisons between the program and a finite-element Poisson-Schrodinger equation solver are performed to validate the program's accuracy.

]]> Richard G. Southwick III et al. Analyzing Dynamic Binary Instrumentation Overhead http://scholarworks.boisestate.edu/cs_facpubs/14 http://scholarworks.boisestate.edu/cs_facpubs/14 Wed, 31 Aug 2011 12:40:56 PDT Robust and powerful software instrumentation tools are essential for dynamic program analysis tasks such as profiling, performance evaluation, and bug detection. Dynamic binary instrumentation (DBI) is a general purpose technique that eases the development of program analysis tools by facilitating automatic low-level instrumentation. DBI-based program analysis can introduce high overhead and it is crucial for tool writers to minimize the cost. Analyzing the performance of instrumentation tools is challenging because most systems use a just-in-time compiler (JIT) to dynamically generate code. In this paper, we describe our method for analyzing the performance of instrumentation tools. The instrumented code is itself instrumented with basic block counters. We implement the profiler in Pin and use it to analyze the behavior of simple and complex instrumentation tools. The analysis yields several unexpected results about the dynamic behavior of instrumented programs. By examining these results, we often find effective solutions to improve performance.

]]> Gang-Ryung Uh et al. Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors http://scholarworks.boisestate.edu/cs_facpubs/13 http://scholarworks.boisestate.edu/cs_facpubs/13 Wed, 31 Aug 2011 12:35:31 PDT To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, often prevent the modulo scheduler from achieving ideal loop initiation intervals. As a result, replicated functional units in multi-issue DSPs are frequently underutilized. In response to this resource underutilization problem, this paper describes a compiler preprocessing strategy that capitalizes on two techniques for effective modulo scheduling, referred to as cloning1 and cloning2. The core of the proposed techniques lies in the direct relaxation of cyclic data dependences by exploiting functional units which are otherwise left unused. Since our preprocessing strategy requires neither code duplication nor additional hardware support, it is relatively easy to implement in DSP compilers. The strategy proposed has been validated by an implementation for a StarCore SC140 optimizing C compiler.

]]> Doosan Cho et al. Code Optimizations for a VLIW-Style Network Processing Unit http://scholarworks.boisestate.edu/cs_facpubs/12 http://scholarworks.boisestate.edu/cs_facpubs/12 Wed, 31 Aug 2011 12:30:04 PDT The explosive growth in network bandwidth and Internet services such as QoS (quality of service) and SLA (service level agreement) monitoring have created the need for new networking hardware called a Network Processing Unit (NPU). In order to rapidly reconfigure the NPU for frequently varying Internet services and technologies, a high-performance C compiler is urgently needed. Several code generation techniques, which are intended to meet the high code quality demands of other types of application specific instruction-set processors (ASIPs) like digital signal processors (DSPs), have already been developed. However, these techniques are insufficient for NPUs due to striking architectural differences such as asymmetric data paths. The main purpose of this paper is to discuss our recent experience with the development of a commercial compiler for a new NPU called the Paion PPII, which is basically a packet engine for NPU to meet the growing need for new high-bandwidth communication equipment targeted for Internet routers and ethernet adapters. For this purpose, we will first show the architectural challenges posed by the target NPU. Then, we will describe several compiler techniques that we found to be effective for the target NPU with various unorthogonal architectural features. The current implementations of the PPII use a VLIW (Very Long Instruction Word) architecture. So, we handled this VLIW-style architecture by employing a simple code compaction scheme which packs multiple parallel instructions into one long instruction word. The experimental results show that our techniques are effective for significantly reducing the dynamic instruction count.

]]> Jinhwan Kim et al. Using Artificial Neural Networks to Identify Headings in Newspaper Documents http://scholarworks.boisestate.edu/cs_facpubs/11 http://scholarworks.boisestate.edu/cs_facpubs/11 Wed, 31 Aug 2011 12:22:21 PDT Several features for Neural Network based document region identification are tested. Specifically, this paper examines features for headline and subheadline region identification. The Neural Network based region identification algorithm is a key component of a document recognition system that segments a document into regions, classifies them into text, graphic, photo, and other region types, and then uses this classification to guide the processing and analysis of the image. The input data are unusually challenging: low quality images of newspaper documents obtained from microfilmed archives. Experiments on several newspaper documents show that the features used are capable of robust and accurate headline identification.

]]> Wei Zhang et al. Efficient and Effective Branch Reordering Using Profile Data http://scholarworks.boisestate.edu/cs_facpubs/10 http://scholarworks.boisestate.edu/cs_facpubs/10 Tue, 30 Aug 2011 15:54:40 PDT The conditional branch has long been considered an expensive operation. The relative cost of conditional branches has increased as recently designed machines are now relying on deeper pipelines and higher multiple issue. Reducing the number of conditional branches executed often results in a substantial performance benefit. This paper describes a code-improving transformation to reorder sequences of conditional branches that compare a common variable to constants. The goal is to obtain an ordering where the fewest average number of branches in the sequence will be executed. First, sequences of branches that can be reordered are detected in the control flow. Second, profiling information is collected to predict the probability that each branch will transfer control out of the sequence. Third, the cost of performing each conditional branch is estimated. Fourth, the most beneficial ordering of the branches based on the estimated probability and cost is selected. The most beneficial ordering often includes the insertion of additional conditional branches that did not previously exist in the sequence. Finally, the control flow is restructured to reflect the new ordering. The results of applying the transformation are on average reductions of about 8%; fewer instructions executed and 13%; branches performed, as well as about a 4%; decrease in execution time.

]]> Minghui Yang et al. Experience with a Retargetable Compiler for a Commercial Network Processor http://scholarworks.boisestate.edu/cs_facpubs/9 http://scholarworks.boisestate.edu/cs_facpubs/9 Tue, 30 Aug 2011 15:43:15 PDT The Paion PPII network processor is designed to meet the growing need for new high bandwidth network equipment. In order to rapidly reconfigure the processor for frequently varying internet services and technologies, a high performance compiler is urgently needed. Albeit various code generation techniques have been proposed for DSPs or ASIPs, we experienced these techniques are not easily tailored towards the target Paion PPII processor due to striking architectural differences. First, we will show the architectural challenges posed by the target processor. Second, novel compiler techniques will be described that effectively exploit unorthogonal architectural features. The techniques include virtual data path, compiler intrinsics, and interprocedural register allocation. Third, intermediate benchmark results will be presented to demonstrate the effectiveness of our techniques.

]]> Jinhwan Kim et al. Improving Low Power Processor Efficiency with Static Pipelining http://scholarworks.boisestate.edu/cs_facpubs/8 http://scholarworks.boisestate.edu/cs_facpubs/8 Wed, 24 Aug 2011 14:19:04 PDT A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. In this paper, we propose to respond to these conflicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefits of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can significantly reduce power consumption without adversely affecting performance.

]]> Ian Finlayson et al. Fast and Stable Conformal Mapping Between a Disc and a Square http://scholarworks.boisestate.edu/cs_facpubs/7 http://scholarworks.boisestate.edu/cs_facpubs/7 Fri, 15 Jul 2011 12:05:50 PDT Mapping between a square or rectangle to a disc or hemisphere, and vice versa, arises in many areas of computer graphics, including environment and reflection mapping, sampling, and BRDFs to name a few. Different maps have different properties: equal-area maps may be more applicable in sampling, while low-distortion or continuity might be preferable in other applications. Conformal mapping preserves angles and thereby locally preserves shape. Although it has been used for over a century, conformal mapping between a disc and a square involves extensive computation with complex numbers. This paper reviews the construction of a conformal map between the unit disc and the unit square, which is formulated as an elliptic integral, and reviews several computational methods. Efficient algorithms are presented for mapping the disc to the square, and from the square to the disc. An implementation is provided in compact C language source code that runs at speeds comparable to simple trigonometric maps.

]]> Michael M. Stark Efficient Construction of Perpendicular Vectors Without Branching http://scholarworks.boisestate.edu/cs_facpubs/6 http://scholarworks.boisestate.edu/cs_facpubs/6 Fri, 15 Jul 2011 11:24:44 PDT This paper presents a novel formula for computing an arbitrary vector perpendicular to a given 3D vector. The formula, as well as the provided C language implementation, are unusual in that they require no conditional branching. The formula involves little arithmetic and is amenable to hardware implementation.

]]> Michael M. Stark Unified Framework for Development, Deployment and Robust Testing of Neuroimaging Algorithms http://scholarworks.boisestate.edu/cs_facpubs/5 http://scholarworks.boisestate.edu/cs_facpubs/5 Wed, 13 Apr 2011 14:35:31 PDT Developing both graphical and commandline user interfaces for neuroimaging algorithms requires considerable effort. Neuroimaging algorithms can meet their potential only if they can be easily and frequently used by their intended users. Deployment of a large suite of such algorithms on multiple platforms requires consistency of user interface controls, consistent results across various platforms and thorough testing.

We present the design and implementation of a novel object-oriented framework that allows for rapid development of complex image analysis algorithms with many reusable components and the ability to easily add graphical user interface controls. Our framework also allows for simplified yet robust nightly testing of the algorithms to ensure stability and cross platform interoperability. All of the functionality is encapsulated into a software object requiring no separate source code for user interfaces, testing or deployment. This formulation makes our framework ideal for developing novel, stable and easy-to-use algorithms for medical image analysis and computer assisted interventions. The technological The framework has been both deployed at Yale and released for public use in the open source multi-platform image analysis software - BioImage Suite (bioimagesuite.org).

]]> Alark Joshi et al. Enforcing Non-Hierarchical Access Policies by Hierarchical Key Assignment Schemes http://scholarworks.boisestate.edu/cs_facpubs/4 http://scholarworks.boisestate.edu/cs_facpubs/4 Thu, 31 Mar 2011 14:37:16 PDT Without proposing a new key assignment scheme, this paper presents a graph translation procedure so that more complicated non-hierarchical access control policies can be enforced by existing hierarchical key assignment schemes.

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