Document Type

Patent

Issued Date

6-17-2003

Assignee

Boise State University

Abstract

This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.

Comments

27 Claims, 21 Drawing Sheets

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